Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
Hardware Software Partitioning Using Genetic Algorithm
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Petri Net Based Approach for Hardware/Software Partitioning
Proceedings of the 14th symposium on Integrated circuits and systems design
Embedded Software for Soc
Energy macromodeling of embedded operating systems
ACM Transactions on Embedded Computing Systems (TECS)
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The hardware-software automated partitioning of a RTOS in the SoC (SoC-RTOS partitioning) is a crucial step in the hardware-software co-design of SoC. First, a new model for SoC-RTOS partitioning is introduced in this paper, which can help in understanding the essence of the SoC-RTOS partitioning. Second, a discrete Hopfield neural network approach for implementing the SoC-RTOS partitioning is proposed, where a novel energy function, operating equation and coefficients of the neural network are redefined. Third, simulations are carried out with comparisons to the genetic algorithm and ant algorithm in the performance and search time used. Experimental results demonstrate the feasibility and effectiveness of the proposed method.