Introduction to real-time software design
Introduction to real-time software design
Instruction-level parallel processing: history, overview, and perspective
The Journal of Supercomputing - Special issue on instruction-level parallelism
Instruction-level parallel processors
Instruction-level parallel processors
Realtime systems
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Embedded Control Systems Development with Giotto
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Patterns for time-triggered embedded systems: building reliable applications with the 8051 family of microcontrollers
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
Safety Critical Computer Systems
Safety Critical Computer Systems
Modern Control Systems
Embedded C
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Rate monotonic vs. EDF: judgment day
Real-Time Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reliable event-triggered systems for mechatronic applications
Journal of Systems and Software - Special issue: Parallel and distributed real-time systems
IEEE Transactions on Computers
A retargetable VLIW compiler framework for DSPs with instruction-level parallelism
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Many single-processor embedded systems are implemented using a time-triggered co-operative (TTC) scheduler. When considering possible alternatives to such a design, one option is a multi-CPU architecture, created using off-the-shelf processors or SoC techniques. In order to allow the rapid assessment of such design alternatives, we are exploring ways in which single-processor TTC code may be “automatically” converted to a multi-CPU equivalent. In this paper, we discuss the design of a prototype source code conversion tool. The input to this tool is the source code for the tasks of a single processor system using a TTC scheduler. The output from the tool (in the current version) is the equivalent multi-processor code based on either a “domino” scheduler or a shared-clock scheduler. In order to assess the effectiveness of the tool, we have used it it in a non-trivial case study: the results from this study are presented in detail.