Evaluating the generalisation capability of a CMOS based synapse

Authors:
A. Ghani;L. McDaid;A. Belatreche;S. Hall;S. Huang;J. Marsland;T. Dowrick;A. Smith
Affiliations:
School of Electrical, Electronic and Computer Engineering, Newcastle University, Newcastle upon Tyne, England NE1 7RU, UK and Intelligent Systems Research Centre, University of Ulster, Magee Campu ...;Intelligent Systems Research Centre, University of Ulster, Magee Campus, Derry BT487JL, N. Ireland, UK;Intelligent Systems Research Centre, University of Ulster, Magee Campus, Derry BT487JL, N. Ireland, UK;Department of Electrical Engineering and Electronics, University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK;Department of Electrical Engineering and Electronics, University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK;Department of Electrical Engineering and Electronics, University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK;Department of Electrical Engineering and Electronics, University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK;Department of Electrical Engineering and Electronics, University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK
Venue:
Neurocomputing
Year:
2012

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Abstract

The focus of this work is to investigate the generalisation capability of compact, solid-state synapses recently proposed by the authors. The synapses can be configured to yield a static or dynamic response. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, are developed and embedded into the neural network toolbox in MATLAB. A network of these synapses was then used to solve benchmark problems using a well-established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.