Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing
Transaction Processing: Concepts and Techniques
Transaction Processing: Concepts and Techniques
Transactional lock-free execution of lock-based programs
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Speculative synchronization: applying thread-level speculation to explicitly parallel applications
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Software transactional memory for dynamic-sized data structures
Proceedings of the twenty-second annual symposium on Principles of distributed computing
Language support for lightweight transactions
OOPSLA '03 Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications
Unbounded Transactional Memory
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Composable memory transactions
Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming
Virtualizing Transactional Memory
Proceedings of the 32nd annual international symposium on Computer Architecture
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Optimizing memory transactions
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Compiler and runtime support for efficient software transactional memory
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Architectural Support for Software Transactional Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Transparently reconciling transactions with locking for java synchronization
ECOOP'06 Proceedings of the 20th European conference on Object-Oriented Programming
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With single thread performance hitting the power wall, hardware architects have turned to chip-level multiprocessing to increase processor performance. As a result, issues related to the construction of scalable and reliable multi-threaded applications have become increasingly important. One of the most pressing problems in concurrent programming has been synchronizing accesses to shared data among multiple concurrent threads. Traditionally, accesses to shared memory have been synchronized using lock-based techniques resulting in scalability, composability and safety problems. Recently, transactional memory has been shown to eliminate many problems associated with lock-based synchronization, and transactional constructs have been added to languages to facilitate programming with transactions. Hardware transactional memory (HTM) is at this point readily available only in the simulated environments. Furthermore, some of the TM systems relying on the hardware support are hybrid solutions that require TM operations to be supported in software as well. Therefore, providing an efficient software transactional memory (STM) implementation has been an important area of research. One of the largest overheads in an STM implementation is incurred in the validation procedure (that is, in ensuring correctness of transactional read operations). This paper presents novel solutions to reduce the validation overhead in an STM. We first present a validation algorithm that is linear in the number of read operations executed by a transaction, and yet does not add any overhead to transactional reads and writes. We then present an algorithm that uses bitmaps to encode information about transactional operations and further reduces both the time and space overheads related to validation. We evaluate the effectiveness of both algorithms in the context of a state-of-the-art STM implementation.