Checking Before Output May Not Be Enough Against Fault-Based Cryptanalysis
IEEE Transactions on Computers
Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Optical Fault Induction Attacks
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Differential Behavioral Analysis
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Practical Setup Time Violation Attacks on AES
EDCC-7 '08 Proceedings of the 2008 Seventh European Dependable Computing Conference
Silicon-level Solutions to Counteract Passive and Active Attacks
FDTC '08 Proceedings of the 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography
Practical Fault Attack on a Cryptographic LSI with ISO/IEC 18033-3 Block Ciphers
FDTC '09 Proceedings of the 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography
On the importance of checking cryptographic protocols for faults
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Design and characterisation of an AES chip embedding countermeasures
International Journal of Intelligent Engineering Informatics
A friendly framework for hidding fault enabled virus for Java based smartcard
DBSec'12 Proceedings of the 26th Annual IFIP WG 11.3 conference on Data and Applications Security and Privacy
COSADE'13 Proceedings of the 4th international conference on Constructive Side-Channel Analysis and Secure Design
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Whilst clock fault attacks are known to be a serious security threat, an in-depth explanation of such faults still seems to be put in order. This work provides a theoretical analysis, backed by practical experiments, explaining when and how clock faults occur. Understanding and modeling the chain of events following a transient clock alteration allows to accurately predict faulty circuit behavior. A prediction fully confirmed by injecting variable-duration faults at predetermined clock cycles. We illustrate the process by successfully attacking an fpga aes implementation using a dll-based fpga platform (one-bit fault attack).