Interconnection networks for large-scale parallel processing: theory and case studies
Interconnection networks for large-scale parallel processing: theory and case studies
Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Cube structures for multiprocessors
Communications of the ACM
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Highly parallel computing (2nd ed.)
Highly parallel computing (2nd ed.)
ACM Transactions on Programming Languages and Systems (TOPLAS)
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
SFCS '87 Proceedings of the 28th Annual Symposium on Foundations of Computer Science
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Interconnection networks are an important and well-studied topic in parallel computing and architecture, but a homogeneous and general method for defining and classifying the topologies and behaviors of interconnection networks is lacking. Topologies are usually specified informally by picture or more formally by permutations of wire enumerations. This paper presents an improved method for specifying multistage networks via permutations, along with two styles of formal functional specification of the entire network, using both a standardmultistage organization and a generalized fat tree organization. This method is applied to two specific indirect multistage switch networks: the baseline and the butterfly. The functional specification emphasizes the similarities between the networks, and also captures the functionality provided by general-purpose network nodes.