Test set selection for structural faults in analog IC's

  • Authors:
  • G. Devarayanadurg;M. Soma;P. Goteti;S. D. Huynh

  • Affiliations:
  • Technol. CAD Dept., Intel Corp., Santa Clara, CA;-;-;-

  • Venue:
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Year:
  • 2006

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Abstract

In this paper, we present methods for constructing optimal tests to detect structural faults in analog integrated circuits in the presence of process variation. The analog test determination problem is formulated as selecting an optimal subset from an initial large set of tests with optimality criteria defined in terms of fault coverage and fault separation on a given fault set. The process variation may be represented either deterministically by box constraints or statistically as random variables. Each of these representations require different methods for computing the detectabilities. In the deterministic case, the detectability measures are computed by a combination of analytical and numerical optimization techniques. Such an approach helps reduce the number of simulations by up to three times over traditional Monte Carlo methods. This approach produces more compact test sets compared to a linear sensitivity analysis while being closer in accuracy to the Monte Carlo method. In the statistical case, the detectability measures are computed as separation distances between the good and faulty distributions. These distributions represented nonparametrically are generated by traditional Monte Carlo techniques. Once the deterministic or statistical detectabilities are computed for the entire test set, a test compaction step is performed which is a covering problem. On solving this covering problem eve get a test set with optimal fault coverage and fault separation