Matched public PUF: ultra low energy security platform
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Differential public physically unclonable functions: architecture and applications
Proceedings of the 48th Design Automation Conference
Integrated circuit security techniques using variable supply voltage
Proceedings of the 48th Design Automation Conference
Device aging-based physically unclonable functions
Proceedings of the 48th Design Automation Conference
Robust passive hardware metering
Proceedings of the International Conference on Computer-Aided Design
Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection
Proceedings of the fifth ACM conference on Security and Privacy in Wireless and Mobile Networks
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry
Proceedings of the 49th Annual Design Automation Conference
Provably complete hardware trojan detection using test point insertion
Proceedings of the International Conference on Computer-Aided Design
Energy attacks and defense techniques for wireless systems
Proceedings of the sixth ACM conference on Security and privacy in wireless and mobile networks
Scalable hardware trojan diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Gate-level characterization (GLC) is the process of quantifying physical and manifestational properties for each gate of an integrated circuit (IC). It is a key step in many IC applications that target cryptography, security, digital rights management, low power, and yield optimization. However, GLC is a challenging task due to the size and structure of modern circuits and insufficient controllability of a subset of gates in the circuit. We have developed a new approach for GLC that employs thermal conditioning to calculate the scaling factors of all the gates by solving a system of linear equations using linear programming (LP). Therefore, the procedure captures the complete impact of process variation (PV). In order to resolve the correlations in the system of linear equations, we expose different gates to different temperatures and thus change their corresponding linear coefficients in the linear equations. We further improve the accuracy of GLC by applying statistical methods in the LP formulation as well as the post-processing steps. In order to enable non-destructive hardware Trojan horse (HTH) detection, we generalize our generic GLC procedure by manipulating the constraint of each linear equation. Furthermore, we ensure the scalability of the approaches for GLC and HTH detection using iterative IC segmentation. We evaluate our approach on a set of ISCAS and ITC benchmarks.