Fairness
Adding liveness properties to coupled finite-state machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
Design and validation of computer protocols
Design and validation of computer protocols
Memory-efficient algorithms for the verification of temporal properties
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Formal Methods in System Design
A new scheme for memory-efficient probabilistic verification
IFIP TC6/ 6.1 international conference on formal description techniques IX/protocol specification, testing and verification XVI on Formal description techniques IX : theory, application and tools: theory, application and tools
Model checking
Randomization Helps in LTL Model Checking
PAPM-PROBMIV '01 Proceedings of the Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification
On the Verification of Temporal Properties
Proceedings of the IFIP TC6/WG6.1 Thirteenth International Symposium on Protocol Specification, Testing and Verification XIII
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
From States to Transitions: Improving Translation of LTL Formulae to Büchi Automata
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
A Nested Depth First Search Algorithm for Model Checking with Symmetry Reduction
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Divide and Compose: SCC Refinement for Language Emptiness
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
On-the-Fly Verification of Linear Temporal Logic
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
Improved Automata Generation for Linear Temporal Logic
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Fast LTL to Büchi Automata Translation
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Reliable Hashing without Collosion Detection
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Algorithmic Verification of Linear Temporal Logic Specifications
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
Directed explicit-state model checking in the validation of communication protocols
International Journal on Software Tools for Technology Transfer (STTT)
Theories of automata on ω-tapes: A simplified approach
Journal of Computer and System Sciences
A light-weight algorithm for model checking with symmetry reduction and weak fairness
SPIN'03 Proceedings of the 10th international conference on Model checking software
A note on on-the-fly verification algorithms
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Fundamenta Informaticae
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We generalize the classic explicit-state emptiness checking algorithm for Büchi word automata (the nested depth-first search) into Büchi automata with multiple acceptance conditions. Avoiding a degeneralization step improves the algorithm's worst-case memory requirements and reduces the worst-case number of state visits during the search. We give experimental results and discuss changes needed to make the generalized algorithmcompatible with well-known probabilistic explicit-state model checking techniques.