Communication-aware Heterogeneous Multiprocessor Mapping for Real-time Streaming Systems

Authors:
Jing Lin;Andreas Gerstlauer;Brian L. Evans
Affiliations:
The University of Texas at Austin, Austin, USA;The University of Texas at Austin, Austin, USA;The University of Texas at Austin, Austin, USA
Venue:
Journal of Signal Processing Systems
Year:
2012

Citing 11
Cited 0

Static scheduling of synchronous data flow programs for digital signal processing

IEEE Transactions on Computers
Evolutionary algorithms for the synthesis of embedded software

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Software Synthesis from Dataflow Graphs

Software Synthesis from Dataflow Graphs
Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip

Proceedings of the conference on Design, automation and test in Europe: Proceedings
SDF^3: SDF For Free

ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip

Journal of Systems Architecture: the EUROMICRO Journal
An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms

Proceedings of the Conference on Design, Automation and Test in Europe
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures

Proceedings of the Conference on Design, Automation and Test in Europe
Embedded System Design: Embedded Systems Foundations of Cyber-Physical Systems

Embedded System Design: Embedded Systems Foundations of Cyber-Physical Systems
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach

IEEE Transactions on Evolutionary Computation
Systematic integration of parameterized local search into evolutionary algorithms

IEEE Transactions on Evolutionary Computation

Quantified Score

Hi-index	0.00

Visualization

Abstract

Real-time streaming signal processing systems typically desire high throughput and low latency. Many such systems can be modeled as synchronous data flow graphs. In this paper, we address the problem of multi-objective mapping of SDF graphs onto heterogeneous multiprocessor platforms, where we account for the overhead of bus-based inter-processor communication. The primary contributions include (1) an integer linear programming (ILP) model that globally optimizes throughput, latency and cost; (2) low-complexity two-stage heuristics based on a combination of an evolutionary algorithm with an ILP to generate either a single sub-optimal mapping solution or a Pareto front for design space optimization. In our simulations, the proposed heuristic shows up to 12x run-time efficiency compared to the global ILP while maintaining a 10驴驴驴6 optimality gap in throughput.