JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures
JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Experimental analysis of sequence dependence on energy saving for error tolerant image processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 46th Annual Design Automation Conference
Computation error analysis in digital signal processing systems with overscaled supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic bit-width adaptation in DCT: an approach to trade off image quality and computation energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process-variation resilient and voltage scalable DCT architecture for robust low-power computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-Level Energy Optimization for Error-Tolerant Image Compression
IEEE Embedded Systems Letters
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This paper presents use of bit truncation and voltage overscaling to reduce the power consumption of JPEG codecs. Both techniques introduce errors which have to be compensated to minimize quality degradation. To handle the errors due to bit truncation, we propose a compensation scheme based on unbiased estimation of the truncation noise. For 4-bit truncation, such a scheme achieves 23% power savings for DCT with only 0.6dB drop in PSNR. To compensate for errors due to aggressive voltage scaling, we introduce an algorithm-specific technique which is based on exploiting the characteristics of the quantized coefficients after zig-zag scan. This technique is very effective in improving the PSNR performance with a small circuit overhead. A combination of the two techniques help achieve even higher power savings with only a modest increase in PSNR. For instance, a combination of 4-bit truncation and operating voltage of 0.78V results in 44% power reduction for DCT with a 1.8dB drop in PSNR performance of the JPEG codec.