Marching cubes: A high resolution 3D surface construction algorithm
SIGGRAPH '87 Proceedings of the 14th annual conference on Computer graphics and interactive techniques
Communications of the ACM
Parallel accelerated isocontouring for out-of-core visualization
PVGS '99 Proceedings of the 1999 IEEE symposium on Parallel visualization and graphics
PVG '01 Proceedings of the IEEE 2001 symposium on parallel and large-data visualization and graphics
Parallel view-dependent isosurface extraction using multi-pass occlusion culling
PVG '01 Proceedings of the IEEE 2001 symposium on parallel and large-data visualization and graphics
A Near Optimal Isosurface Extraction Algorithm Using the Span Space
IEEE Transactions on Visualization and Computer Graphics
The asymptotic decider: resolving the ambiguity in marching cubes
VIS '91 Proceedings of the 2nd conference on Visualization '91
VIS '94 Proceedings of the conference on Visualization '94
A novel approach to extract triangle strips for iso-surfaces in volumes
VRCAI '04 Proceedings of the 2004 ACM SIGGRAPH international conference on Virtual Reality continuum and its applications in industry
Efficient Parallel Out-of-core Isosurface Extraction
PVG '03 Proceedings of the 2003 IEEE Symposium on Parallel and Large-Data Visualization and Graphics
Improving parallel data transfer times using predicted variances in shared networks
CCGRID '05 Proceedings of the Fifth IEEE International Symposium on Cluster Computing and the Grid (CCGrid'05) - Volume 2 - Volume 02
IEEE Transactions on Visualization and Computer Graphics
Fast remote isosurface visualization with chessboarding
EG PGV'04 Proceedings of the 5th Eurographics conference on Parallel Graphics and Visualization
Case study of multithreaded in-core isosurface extraction algorithms
EG PGV'04 Proceedings of the 5th Eurographics conference on Parallel Graphics and Visualization
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A scheme for improving the efficiency of parallel isosurfacing for very large datasets is presented. The scheme is aimed at improving performance in multi-processor environments, especially for environments in which interprocessor communication limitations become a bottleneck, such as when the number of processors can scale up without commensurate scale up in inter-processor communication bandwidth. The scheme enables load-balanced computation while also limiting unnecessary communication between processors through the use of communication piggybacking and interleaving. Empirical results are also presented and suggest that the scheme reduces communication by about 15% and overall isosurfacing time by about 13% over a highly efficient non-piggybacked parallel isosurfacing approach.