Analog methods for computer-aided circuit analysis & diagnosis
Analog methods for computer-aided circuit analysis & diagnosis
A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
An algorithm for multiple fault diagnosis in analogue circuits: Research Articles
International Journal of Circuit Theory and Applications
Printed Circuits Handbook
Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits
Journal of Electronic Testing: Theory and Applications
Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
A method for fast simulation of multiple catastrophic faults in analogue circuits
International Journal of Circuit Theory and Applications
Improved analogue fault coverage estimation using probabilistic analysis
International Journal of Circuit Theory and Applications
| Hi-index | 0.00 |
This paper deals with the diagnosis of multiple catastrophic faults, being cuts (open-circuits) of some connecting paths and/or short-circuits of some pairs of points in analog circuits. A method enabling us to detect and identify the faults, taking into account the deviations of the circuit parameters within their tolerance ranges, is developed. The method exploits an appropriate fault dictionary. The fault dictionary is used only for preliminary identification of the faults, because it is based on the analysis of the circuits with nominal parameters. The crucial point of the method is a verification procedure, proposed in this paper, based on the linear programming approach. It leads to the results considering the component variations within their tolerance ranges. In addition, a procedure for selecting appropriate test points, employing some evolutionary techniques, is developed. Although the approach presented in this paper is described in detail for linear circuits, it can be directly generalized to nonlinear circuits. Three numerical examples, including two linear and one nonlinear circuits, illustrate the proposed method and show its efficiency. Copyright © 2011 John Wiley & Sons, Ltd.