Direct memory access optimization in wireless terminals for reduced memory latency and energy consumption

Authors:
Miguel Peon-Quiros;Alexandros Bartzas;Stylianos Mamagkakis;Francky Catthoor;Jose M. Mendias;Dimitrios Soudris
Affiliations:
DACYA/UCM, Madrid, Spain;VLSI Design Center, Democritus Univ. Thrace, Xanthi, Greece;IMEC vzw, Heverlee, Belgium;IMEC vzw, Heverlee and Katholieke Universiteit Leuven, Belgium;DACYA/UCM, Madrid, Spain;VLSI Design Center, Democritus Univ. Thrace, Xanthi, Greece
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

Today, wireless networks are becoming increasingly ubiquitous. Usually several complex multi-threaded applications are mapped on a single embedded system and all of them are triggered by a single wireless stream (which corresponds to the dynamic run-time behavior of the user). It is almost impossible to analyze these systems fully at design-time. Therefore, run-time information has also to be used in order to produce an efficient design. This introduces new challenges, especially for embedded system designers using a Direct Memory Access (DMA) module, who have to know in advance the memory transfer behavior of the whole system, in order to design and program their DMA efficiently. In this paper, we propose a mixed Hardware/Software optimization at system level. More specifically, we propose to adapt DMA usage parameters automatically at run-time based on online information. With our proposed optimization approach we manage to reduce the mean latency of the memory transfers while optimizing energy consumption and system responsiveness. We evaluate our approach using a set of real-life applications and real wireless dynamic streams.