On two-pronged power-aware voltage scheduling for multi-processor real-time systems

Authors:
Naotake Kamiura;Teijiro Isokawa;Nobuyuki Matsui
Affiliations:
Graduate School of Engineering, University of Hyogo, Himeji, Japan;Graduate School of Engineering, University of Hyogo, Himeji, Japan;Graduate School of Engineering, University of Hyogo, Himeji, Japan
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

A power-aware voltage-scheduling heuristic is presented for a hard real-time multi-processor system. Given a task graph, the offline component first allocates a certain percentage of worst-case execution units of some tasks to them as potions to be executed in a higher voltage. Once some path is speeded up, the rest of the offline component chooses and speeds up one of the paths sharing tasks with that path. The online component reclaims the slack, which occurs when some task actually finishes, to slow down the execution speed of its successor. Experimental results are finally provided to demonstrate the effectiveness of the proposed heuristic.