VHDL based design of graphics ASICs

  • Authors:

  • M. White;G. J . Dunnett;P. F. Lister;R. L. Grimsdale

  • Affiliations:

  • VLSI and Computer Graphics Research Group, School of Engineering, University of Sussex, Brighton, England;VLSI and Computer Graphics Research Group, School of Engineering, University of Sussex, Brighton, England;VLSI and Computer Graphics Research Group, School of Engineering, University of Sussex, Brighton, England;VLSI and Computer Graphics Research Group, School of Engineering, University of Sussex, Brighton, England

  • Venue:
  • EGGH'93 Proceedings of the Eighth Eurographics conference on Graphics Hardware
  • Year:
  • 1993

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Abstract

The design of graphics ASICs for geometry and rasterisation processing has traditionally involved the use of schematic design entry whereby functional blocks are netlisted and instantiated on the schematic. This methodology is fine at the top most hierarchical levels of a design but becomes tedious and error prone at the lower gate levels. Often these designs are targetted at custom ASICs through the use of silicon compiler technology. Unfortunately, this is an expensive and risky approach to implementing these ASICs, particularly for University research laboratories where additional funding may not be available to cover non-recurring engineering costs, such as multiple mask runs, which may be needed due to design errors. This paper presents an alternative to these traditional approachs. A new approach, top down ASIC design with logic synthesis and optimisation targetting FPGA ASICs, is presented . We demonstrate through some examples of our texturing and scan conversion hardware the benefits of this new approach.