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A data locality optimizing algorithm
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Data transformations for eliminating conflict misses
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A compiler technique for improving whole-program locality
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Efficient Parallelization using Combined Loop and Data Transformations
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Custom Data Layout for Memory Parallelism
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Integrating loop and data optimizations for locality within a constraint network based framework
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Cache topology aware computation mapping for multicores
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A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
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Automatic Loop Tiling for Direct Memory Access
IPDPS '11 Proceedings of the 2011 IEEE International Parallel & Distributed Processing Symposium
Optimizing Data Layouts for Parallel Computation on Multicores
PACT '11 Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques
Optimizing data locality using array tiling
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Proceedings of the International Conference on Computer-Aided Design
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Motivated by the observation that most existing data locality optimizations do not specifically target shared last-level caches of emerging multicores and that even multicore-specific locality-oriented techniques employ either loop or data layout optimizations but not both, in this paper we present an integrated loop and data layout optimization strategy, with the goal of improving the last-level cache performance of multicores that execute multithreaded applications. We present a detailed mathematical formulation of our locality optimization strategy and present experimental data from our current implementation. Our results, collected using 14 application programs, clearly show that the proposed integrated approach is very successful in practice, and outperforms both pure loop optimization and pure data layout optimization based alternatives. Our results also indicate that the savings achieved increase with increased core count and larger data set sizes.