ECL: a specification environment for system-level design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Compilation techniques for parallel systems
Parallel Computing - Special Anniversary issue
System Design with SystemC
REFLIX: A Processor Core for Reactive Embedded Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
REMIC: design of a reactive embedded microprocessor core
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
WCET analysis for a Java processor
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
Modeling Embedded Systems: From SystemC and Esterel to DFCharts
IEEE Design & Test
SystemJ compilation using the tandem virtual machine approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems
A new multithreaded architecture supporting direct execution of Esterel
EURASIP Journal on Embedded Systems
SystemJ: A GALS language for system level design
Computer Languages, Systems and Structures
Esterel v7: from verified formal specification to efficient industrial designs
FASE'05 Proceedings of the 8th international conference, held as part of the joint European Conference on Theory and Practice of Software conference on Fundamental Approaches to Software Engineering
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a new heterogeneous multiprocessor (GALS-HMP) for the execution of Globally Asynchronous Locally Synchronous (GALS) programming languages. It specifically targets SystemJ GALS language, which extends Java with asynchronous and synchronous concurrency. A SystemJ program is partitioned by a compiler onto data-driven and control-driven parts, which are then allocated for the execution on traditional and reactive processors, which constitute GALS-HMP. The reactive processor is customized to meet the requirements of the control parts of the SystemJ programs. The prototypes developed on an FPGA show significant improvements in code size and execution speed compared to the case of using just traditional processors.