Current trends in concurrency. Overviews and tutorials
Statecharts: A visual formalism for complex systems
Science of Computer Programming
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Customized instruction-sets for embedded processors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Flexible instruction processors
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
CCSimP - An Instruction-level Custom-Configurable Processor for FPLDs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
SystemJ compilation using the tandem virtual machine approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A power-efficient processor core for reactive embedded applications
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
GALS-HMP: A heterogeneous multiprocessor for embedded applications
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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Efficient and reliable interaction with the environment (reactivity) is a key feature for many embedded system applications. Current implementation technologies that include standard microprocessors and microcontrollers, or fully customized systems, are not ideally suited to such reactive tasks. We propose novel microprocessor architecture that has native support for reactivity, with the flexibility to be customized at much higher level than usual microprocessor-based solutions. The proposed microprocessor architecture is an extension of our existing FLIX processor open core. The new processor core, called REFLIX (Reactive FLIX), guarantees at most one instruction cycle delay for priority resolution and preemption and supports design style for reactive applications used in Esterel programming language.