CCS '99 Proceedings of the 6th ACM conference on Computer and communications security
Building a high-performance, programmable secure coprocessor
Computer Networks: The International Journal of Computer and Telecommunications Networking - Special issue on computer network security
Architectural support for copy and tamper resistant software
ACM SIGPLAN Notices
Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
SIAM Journal on Computing
CRYPTO '01 Proceedings of the 21st Annual International Cryptology Conference on Advances in Cryptology
Controlled Physical Random Functions
ACSAC '02 Proceedings of the 18th Annual Computer Security Applications Conference
Architecture for Protecting Critical Secrets in Microprocessors
Proceedings of the 32nd annual international symposium on Computer Architecture
Secure untrusted data repository (SUNDR)
OSDI'04 Proceedings of the 6th conference on Symposium on Opearting Systems Design & Implementation - Volume 6
Hardware-rooted trust for secure key management and transient trust
Proceedings of the 14th ACM conference on Computer and communications security
How low can you go?: recommendations for hardware-supported minimal TCB code execution
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Flicker: an execution infrastructure for tcb minimization
Proceedings of the 3rd ACM SIGOPS/EuroSys European Conference on Computer Systems 2008
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
IEEE Transactions on Computers
Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Reconfigurable Physical Unclonable Functions - Enabling technology for tamper-resistant storage
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
AEGIS: A single-chip secure processor
Information Security Tech. Report
New shielding functions to enhance privacy and prevent misuse of biometric templates
AVBPA'03 Proceedings of the 4th international conference on Audio- and video-based biometric person authentication
TrustVisor: Efficient TCB Reduction and Attestation
SP '10 Proceedings of the 2010 IEEE Symposium on Security and Privacy
Cryptographic extraction and key derivation: the HKDF scheme
CRYPTO'10 Proceedings of the 30th annual conference on Advances in cryptology
SecureME: a hardware-software approach to full system security
Proceedings of the international conference on Supercomputing
Memoir: Practical State Continuity for Protected Modules
SP '11 Proceedings of the 2011 IEEE Symposium on Security and Privacy
CPU support for secure executables
TRUST'11 Proceedings of the 4th international conference on Trust and trustworthy computing
TPM-SIM: a framework for performance evaluation of trusted platform modules
Proceedings of the 48th Design Automation Conference
Read-proof hardware from protective coatings
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Cloud Data Protection for the Masses
Computer
Secure remote authentication using biometric data
EUROCRYPT'05 Proceedings of the 24th annual international conference on Theory and Applications of Cryptographic Techniques
Robust fuzzy extractors and authenticated key agreement from close secrets
CRYPTO'06 Proceedings of the 26th annual international conference on Advances in Cryptology
SP '12 Proceedings of the 2012 IEEE Symposium on Security and Privacy
CARMA: a hardware tamper-resistant isolated execution environment on commodity x86 platforms
Proceedings of the 7th ACM Symposium on Information, Computer and Communications Security
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We present OASIS, a CPU instruction set extension for externally verifiable initiation, execution, and termination of an isolated execution environment with a trusted computing base consisting solely of the CPU. OASIS leverages the hardware components available on commodity CPUs to achieve a low-cost, low-overhead design.