Quantum computation and quantum information
Quantum computation and quantum information
Proceedings of the 7th Colloquium on Automata, Languages and Programming
A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
Architectural implications of quantum computing technologies
ACM Journal on Emerging Technologies in Computing Systems (JETC)
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Reducing Reversible Circuit Cost by Adding Lines
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates
ISMVL '11 Proceedings of the 2011 41st IEEE International Symposium on Multiple-Valued Logic
RevKit: an open source toolkit for the design of reversible circuits
RC'11 Proceedings of the Third international conference on Reversible Computation
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantum Circuit Simplification and Level Compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Synthesis Flow for Sequential Reversible Circuits
ISMVL '12 Proceedings of the 2012 IEEE 42nd International Symposium on Multiple-Valued Logic
Depth-optimized reversible circuit synthesis
Quantum Information Processing
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The synthesis of Boolean functions, as they are found in many quantum algorithms, is usually conducted in two steps. First, the function is realized in terms of a reversible circuit followed by a mapping into a corresponding quantum realization. During this process, the number of lines and the quantum costs of the resulting circuits have mainly been considered as optimization objectives thus far. However, beyond that also the depth of a quantum circuit is vital. Although first synthesis approaches that consider depth have recently been introduced, the majority of design methods did not consider this metric. In this paper, we introduce an optimization approach aiming for the reduction of depth in the process of mapping a reversible circuit into a quantum circuit. For this purpose, we present an improved (local) mapping of single gates as well as a (global) optimization scheme considering the whole circuit. In both cases, we incorporate the idea of exploiting additional circuit lines which are used in order to split a chain of serial gates. Our optimization techniques enable a concurrent application of gates which significantly reduces the depth of the circuit. Experiments show that reductions of approx. 40% on average can be achieved when following this scheme.