Multi-character cost-effective and high throughput architecture for content scanning

  • Authors:
  • José M. Bande;José Hernández Palancar;René Cumplido

  • Affiliations:
  • -;-;-

  • Venue:
  • Microprocessors & Microsystems
  • Year:
  • 2013

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Abstract

String matching is a time and resource consuming operation that lies at the core of Network Intrusion Detection Systems. In this paper a method and corresponding hardware architecture for string matching is presented. The proposed method is composed of two main steps. The first step performs a pre-detection of signatures alignment, and in the second step the alignment is corrected and the signatures are detected by a matcher. The compact and efficient architecture is designed to share resources among several modules that perform the detection and correction step needed for the string matching. Implementation results in a FPGA Virtex5 device show that the proposed architecture can perform string matching with a database with more than 400K characters. And is also capable of achieving speeds of more than 30Gbps, which is much higher that previous works reported in the literature.