Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs

Authors:
Zachary K. Baker;Viktor K. Prasanna
Affiliations:
IEEE;IEEE
Venue:
IEEE Transactions on Dependable and Secure Computing
Year:
2006

Citing 9
Cited 5

String matching on multicontext FPGAs using self-reconfiguration

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A compiler approach to fast hardware design space exploration in FPGA-based systems

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Granidt: Towards Gigabit Rate Network Intrusion Detection Technology

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
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Fast Regular Expression Matching Using FPGAs

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SPANIDS: a scalable network intrusion detection loadbalancer

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A memory-efficient pipelined implementation of the aho-corasick string-matching algorithm

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Abstract

This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and tree-based lookahead architectures. Intrusion detection for network security is a compute-intensive application demanding high system performance. The tools implement and automate a customizable flow for the creation of efficient Field Programmable Gate Array (FPGA) architectures using system-level optimizations. Our methodology allows for customized performance through more efficient communication and extensive reuse of hardware components for dramatic increases in area-time performance.