The Mathematics of the Pentium Division Bug
SIAM Review
The AETG System: An Approach to Testing Based on Combinatorial Design
IEEE Transactions on Software Engineering
Factor-covering designs for testing software
Technometrics
In-Parameter-Order: A Test Generation Strategy for Pairwise Testing
HASE '98 The 3rd IEEE International Symposium on High-Assurance Systems Engineering
Determination of Test Configurations for Pair-Wise Interaction Coverage
TestCom '00 Proceedings of the IFIP TC6/WG6.1 13th International Conference on Testing Communicating Systems: Tools and Techniques
An Investigation of the Applicability of Design of Experiments to Software Testing
SEW '02 Proceedings of the 27th Annual NASA Goddard Software Engineering Workshop (SEW-27'02)
A Measure for Component Interaction Test Coverage
AICCSA '01 Proceedings of the ACS/IEEE International Conference on Computer Systems and Applications
Designs, Codes and Cryptography
The Art of Computer Programming, Volume 4, Fascicle 3: Generating All Combinations and Partitions
The Art of Computer Programming, Volume 4, Fascicle 3: Generating All Combinations and Partitions
One-test-at-a-time heuristic search for interaction test suites
Proceedings of the 9th annual conference on Genetic and evolutionary computation
ICSTW '09 Proceedings of the IEEE International Conference on Software Testing, Verification, and Validation Workshops
Combining Satisfiability Solving and Heuristics to Constrained Combinatorial Interaction Testing
TAP '09 Proceedings of the 3rd International Conference on Tests and Proofs
Randomized Postoptimization of Covering Arrays
Combinatorial Algorithms
Test Generation with Context Free Grammars and Covering Arrays
TAIC-PART '09 Proceedings of the 2009 Testing: Academic and Industrial Conference - Practice and Research Techniques
Covering and radius-covering arrays: Constructions and classification
Discrete Applied Mathematics
A survey of methods for constructing covering arrays
Programming and Computing Software
Vector sets for exhaustive testing of logic circuits
IEEE Transactions on Information Theory
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Covering arrays are used for generating tests for interfaces with a large number of parameters. In this paper, a new method is described for constructing homogeneous and heterogeneous covering arrays that is based on a combination of combinatorial and optimization methods. In a wide class of particular cases, the method speeds up the construction of arrays several times (depending on a particular case) compared with well-known, widely used optimization methods. In most cases, the sizes of the arrays obtained are approximately the same as those of the arrays constructed by other optimization methods; in a number of particular cases, one could obtain arrays that are smaller by 5---15%. The application range of the new method is analyzed.