The Distribution of Waiting Times in Clocked Multistage Interconnection Networks
IEEE Transactions on Computers
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
On the validity of trace-driven simulation for multiprocessors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Synthetic Traces for Trace-Driven Simulation of Cache Memories
IEEE Transactions on Computers
Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
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New networks, called GLO networks, are constructed by adding bus-like links to omega networks, providing additional capacity between cells on momentarily busy paths. Equivalent pin-count GLO and omega networks offered uniform and nonuniform traffic were simulated. GLO networks exhibited lower latency for nonuniform traffic and light to moderate uniform traffic.