Instruction scheduling and executable editing

  • Authors:

  • Eric Schnarr;James R. Larus

  • Affiliations:

  • Computer Sciences Department, University of Wisconsin-Madison, 1210 West Dayton Street, Madison, WI;Computer Sciences Department, University of Wisconsin-Madison, 1210 West Dayton Street, Madison, WI

  • Venue:
  • Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
  • Year:
  • 1996

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Abstract

Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and actual performance, while frustrating for computer architects and chip manufacturers, opens the exciting possibility of low-cost instrumentation for measurement, simulation, or emulation. Instrumentation code that executes in previously unused processor cycles is effectively hidden. On two superscalar SPARC processors, a simple, local scheduler hid an average of 14% of the overhead cost of profiling instrumentation in the SPECINT benchmarks and an average of 30% of the profiling cost in the SPECFP benchmarks.