A novel predictable segmented FPGA routing architecture

Authors:
Emil S. Ochotta;Patrick J. Crotty;Charles R. Erickson;Chih-Tsung Huang;Rajeev Jayaraman;Richard C. Li;Joseph D. Linoff;Luan Ngo;Hy V. Nguyen;Kerry M. Pierce;Douglas P. Wieland;Jennifer Zhuang;Scott S. Nance
Affiliations:
Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA;Xilinx, Inc., 2100 Logic Drive, San Jose, CA
Venue:
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Year:
1998

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Abstract

In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures allow much flexibility in routing, but incur large delay penalties when a signal has high fanout or must traverse medium to long distances to reach its target. Reducing the number of programmable interconnect points (PIPs) that a signal must traverse to reach its target, while eliminating the RC delay buildup due to signal fanout, improves design performance and offers highly predictable signal delays.