Using Emulations to Enhance the Performance of Parallel Architectures

• Authors: Bojana Obernić;Martin C. Herbordt;Arnold L. Rosenberg;Charles C. Weems
• Venue: IEEE Transactions on Parallel and Distributed Systems
• Year: 1999

We illustrate the potential of techniques and results from the theory of network emulations to enhance the performance of a parallel architecture. The vehicle for this demonstration is a suite of algorithms that endow an $N$-processor bit-serial processor array ${\cal A}$ with a 驴meta-instruction驴GAUGE$k$, which (logically) reconfigures ${\cal A}$ into an $N/k$-processor virtual machine ${\cal B}_k$ that has: 1) a datapath and memory bus whose emulated width is $k$ bits, as opposed to ${\cal A}$'s 1-bit width and 2) an instruction set that operates on $k$-bit words, in contrast to ${\cal A}$'s instruction set, which operates on 1-bit words. In order to stress the strength of the approach, we show (via pseudocode) how our emulation techniques can be implemented efficiently even if ${\cal A}$ operates in strict SIMD mode, with only single-bit masking capabilities and with no indexed memory accesses. We describe at an algorithmic level how to implement our technique驴including datapath conversion (驴corner-turning驴) and the creation of the word-parallel instruction sets驴on arrays of any regular network topology. We instantiate our technique in detail for arrays based on topologies with quite disparate characteristics: the hypercube, the de Bruijn network, and a genre of mesh with reconfigurable buses. Importantly, the emulations that underlie our technique do not alter the native machine's instruction set, hence allowing an invariant programming model across gauges.