A Circuit Architecture for Analog On-Chip Back Propagation Learning with Local Learning Rate Adaptation

Authors:
G. M. Bo;D. D. Caviglia;H. Chiblè;M. Valle
Affiliations:
Department of Biophysical and Electronic Engineering University of Genoa, Via all’Opera Pia 11/A, 16145 Genova, Italy gian_bo@dibe.unige.it;Department of Biophysical and Electronic Engineering University of Genoa, Via all’Opera Pia 11/A, 16145 Genova, Italy;Department of Biophysical and Electronic Engineering University of Genoa, Via all'Opera Pia 11/A, 16145 Genova, Italy;Department of Biophysical and Electronic Engineering University of Genoa, Via all’Opera Pia 11/A, 16145 Genova, Italy
Venue:
Analog Integrated Circuits and Signal Processing - Special issue on Learning on Silicon
Year:
1999

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Abstract

In this paper we present the analog CMOS architecture of a Multi Layer Perceptron network with on-chip stochastic Back Propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient (i.e. fast convergence speed) with respect to similar architectures presented in the literature. Circuit simulation results on the XOR learning problem validate the network behavior.