Analog VLSI hardware implementation of a supervised learning algorithm

Authors:
Gian Marco Bo;Daniele Caviglia;Hussein Chiblé;Maurizio Valle
Affiliations:
Univ. of Genoa, Genoa, Italy;Univ. of Genoa, Genoa, Italy;Univ. of Genoa, Genoa, Italy;Univ. of Genoa, Genoa, Italy
Venue:
Hardware implementation of intelligent systems
Year:
2001

Citing 13
Cited 0

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Abstract

In this chapter, we introduce an analog chip hosting a self-learning neural network with local learning rate adaptation. The neural architecture has been validated through intensive simulations on the recognition of handwritten characters. It has hence been mapped onto an analog architecture. The prototype chip implementing the whole on-chip learning neural architecture has been designed and fabricated by using a 0.7 &mgr;m channel length CMOS technology. Experimental results on two learning tasks confirm the functionality of the chip and the soundness of the approach. The chip features a peak performance of 2.65 x 106 connections updated per second.