Analog VLSI hardware implementation of a supervised learning algorithm
Hardware implementation of intelligent systems
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Analog Integrated Circuits and Signal Processing
An Experimental Analog CMOS Self-Learning Chip
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
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Analog implementations of neural networks and other computing architectures have gained increasing interest over the last decade. The field is at a critical juncture: continued interest will depend on the ability to demonstrate a clear advantage over digital solutions to problems of commercial interest. The neural network design group at SGS-Thomson Microelectronics has been working to explore the advantages and limitations of analog computation and implementations of neural network architectures. We are investigating 3 large-scale analog VLSI chips, all of which work on problems in image processing. The use of analog computing arrays, because of their efficiency and regularity, have formed the basis of most of our designs, while several different computing modes, including current, charge, and conductance have been explored. Another area in which we have focused is on the use of floating-gate flash-EEPROM devices for both non-volatile analog storage and computation. This paper will share insights into the lessons we have learned, the results we have achieved, and the limitations we have encountered. Particular emphasis will be made on two subjects: computational efficiency and equivalent precision of array-based analog computing circuits.