Scheduling of outputs in grammar-based hardware synthesis of data communication protocols

  • Authors:
  • J. Öberg;A. Kumar;A. Hemani

  • Affiliations:
  • Electronic Systems Design Laboratory, Royal Institute of Technology (KTH), ESDLab/KTH-Electrum, Electrum 229, S-164 40 Kista, Sweden;Dept. of Computer Science & Engineering, Indian Institute of Technology, New Delhi, India;Electronic Systems Design Laboratory, Royal Institute of Technology (KTH), ESDLab/KTH-Electrum, Electrum 229, S-164 40 Kista, Sweden

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 1998

Quantified Score

Hi-index 0.00

Visualization

Abstract

We present a grammar based specification method for hardware synthesis of data communication protocols in which the specification is independent of the port size. Instead, it is used during the synthesis process as a constraint. When the width of the output assignments exceed the chosen out-put port width, the assignments are split and scheduled over the available states. We present a solution to this problem and results of applying it to some relevant problems.