Discrete-time signal processing
Discrete-time signal processing
Impulse response fault model and fault extraction for functional level analog circuit diagnosis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Integration of IEEE Std. 1149.1 and Mixed-Signal Test Architectures
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proposal to Simplify Development of a Mixed-Signal Test Standard
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Method of Extending an 1149.1 Bus for Mixed-Signal Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Structure and Metrology for an Analog Testability Bus
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Towards a Test Standard for Board and System Level Mixed-Signal Interconnects
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Structure and Metrology for a Single-wire Analog
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Hi-index | 0.00 |
A parasitic effect removal methodology is proposed to handle the large parasitic effects in analog testability buses. The removal is done by an on-chip test generation technique and an intrinsic response extraction algorithm. On-chip test generation creates test signals on-chip to avoid the parasitic effects of the test application bus. The intrinsic response extraction cross-checks and cancels the parasitic effects of both test application and response observation paths. The tests using both SPICE simulation and MNABST-1 P1149.4 test chip reveal that the proposed algorthm can not only remove the parasitic effects of the test buses but also tolerate test signal variations. Furthermore, it is robust enough to handle loud environmental noise and the nonlinearity of the switching devices.