Low Power Digital CMOS Design
Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35͘m CMOS technology
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A 4.1 GHz prescaler using double data throughput E-TSPC structures
Proceedings of the 20th annual conference on Integrated circuits and systems design
Design of high speed digital circuits with E-TSPC cell library
Proceedings of the 24th symposium on Integrated circuits and systems design
Low voltage and low power divide-by-2/3 counter design using pass transistor logic circuit technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock (TSPC) [1], [2], are presented. These structures, formed by the connection of proper data paths, allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing such structures are shortly reported and to illustrate more complex applications, the design of a dual-modulus prescaler (divide by 128/129) in a 0.8 µm CMOS process is fully depicted. This prescaler, according to simulations, reaches a maximum 2.19-GHz operation rate at 5 V with a 46 mW power consumption. This new approach is also compared with a previous design (implemented with the E-TSPC technique and attaining a 1.59 GHz operation rate) and with other recently published circuits.