Design and Self-Test for Switched-Current Building Blocks

  • Authors:
  • Thomas Olbrich;Andrew Richardson

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Design & Test
  • Year:
  • 1996

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Abstract

Switched-current designs are receiving increasing interest within the VLSI community as the technique allowing analogue functions to be implemented on a digital process. In addition, switched-current designs tend to be robust and compatible with the trend for reduced supply voltages. This article describes the design of a novel type of switched-current memory cell with a built-in-self-test option. The cell is digitally controlled and can be used as a building block for a range of analogue functions. A divide-by-two circuit for reference signal generation in algorithmic A-to-D converters is given as an example application.Furthermore, two self-test approaches for these building blocks are described and their effectiveness evaluated. Over 3000 single faults have been simulated in HSPICE to obtain the fault coverage using an open/short fault model. The self-test functions are easy to apply, need only a very small overhead and result in fault coverages up to 95% for shorts and 60% for open-circuits.The analysis of undetected faults revealed that certain circuit structures used in the demonstrators which are common to analogue and mixed-signal designs are practically untestable.