Design, characterization & modelling of a CMOS magnetic field sensor
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Microsystems testing: an approach and open problems
Proceedings of the conference on Design, automation and test in Europe
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
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IEEE Design & Test
Proceedings of the IEEE International Test Conference
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Proceedings of the IEEE International Test Conference
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ITC '98 Proceedings of the 1998 IEEE International Test Conference
MEMS fault model generation using CARAMEL
ITC '98 Proceedings of the 1998 IEEE International Test Conference
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ITC '98 Proceedings of the 1998 IEEE International Test Conference
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EDTC '96 Proceedings of the 1996 European conference on Design and Test
Defect-Oriented Experiments in Fault Modelling and Fault Simulation of Microsystem Components
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Pseudorandom functional BIST for linear and nonlinear MEMS
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Electro-thermal Stimuli for MEMS Testing in FSBM Technology
Journal of Electronic Testing: Theory and Applications
Built-in-self-test techniques for MEMS
Microelectronics Journal
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This paper addresses MEMS testing through a case study: a micromachined magnetic field sensor with on-chip electronics. The sensor element is based on a cantilever beam that is deflected by means of the Lorentz force. Embedded piezoresistors are used to detect strain in the cantilever beam and thus to detect the magnetic field. A test approach is presented for the whole system focussing on fault classification, on design for testability and on production test costs. Fault classification introduces several catastrophic and parametric faults on both mechanical and electrical elements. Simple and low-cost design for testability such as test point insertion is then discussed for test cost reduction and for fault coverage enhancement.