Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Analog VLSI and neural systems
Analog VLSI and neural systems
Introduction to programmable active memories
Systolic array processors
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Programmable active memories: a performance assessment
Proceedings of the 1993 symposium on Research on integrated systems
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Type checking higher-order polymorphic multi-methods
Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Finite Digital Synchronous Circuits Are Characterized by 2-Algebraic Truth Tables
ASIAN '00 Proceedings of the 6th Asian Computing Science Conference on Advances in Computing Science
Synchronization of periodic clocks
Proceedings of the 5th ACM international conference on Embedded software
N-synchronous Kahn networks: a relaxed model of synchrony for real-time systems
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Universal Hard Interaction for Clockless Computation: Dem Glücklichen schlägt keine Stunde!
Fundamenta Informaticae - Machines, Computations and Universality, Part II
An embedded declarative data transformation language
PPDP '09 Proceedings of the 11th ACM SIGPLAN conference on Principles and practice of declarative programming
Declarative modeling of finite mathematics
Proceedings of the 12th international ACM SIGPLAN symposium on Principles and practice of declarative programming
Universal Hard Interaction for Clockless Computation: Dem Glücklichen schlägt keine Stunde!
Fundamenta Informaticae - Machines, Computations and Universality, Part II
Iterating invertible binary transducers
DCFS'12 Proceedings of the 14th international conference on Descriptional Complexity of Formal Systems
Synchronous digital circuits as functional programs
ACM Computing Surveys (CSUR)
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We establish new, yet intimate relationships between the 2-adic integers /sub 2/Z from arithmetics and digital circuits, both finite and infinite, from electronics. 1) Rational numbers with an odd denominator correspond to output only synchronous circuits. 2) Bit-wise 2-adic mappings correspond to combinational circuits. 3) Online functions /spl forall/n/spl isin/N,x/spl isinsub 2/Z:f(x)=f(xmodd2/sup n/)mod2/sup n/), correspond to synchronous circuits. 3) Continuous functions, /sub 2/Z/spl rarrsub 2/Z, correspond to circuits with output enable. The proof is obtained by constructing synchronous decision diagrams SDDs. They generalize to sequential circuits as classical BDD constructs do for combinational circuits. From simple identities over /sub 2/Z, we derive both classical and new bit-serial circuits for computing: {+,-,/spl times/,1/(1-2x), (1+8x)}. The correctness of each circuit directly follows from the 2-adic definition of the corresponding operator. All but the adders (+,-) above are infinite. Yet the use of reset signals reduces all previously infinite operators to finite circuits. The present work lays out the semantic basis of a new language for describing synchronous circuits. Language 2Z incorporates arithmetic synthesis for some of the above bit-serial operators, and for periodic binary constants (logic from chronograms). It also provides for the powerful deeply binding synchronous enable and reset operators, whose meaning is discussed.