Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Issues in the architecture of direct interconnection schemes for multiprocessors
Issues in the architecture of direct interconnection schemes for multiprocessors
A comparison of sorting algorithms for the connection machine CM-2
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
A performance study of wormhole routed networks through analytical modeling and experimentation
A performance study of wormhole routed networks through analytical modeling and experimentation
A VLSI Architecture for Concurrent Data Structures
A VLSI Architecture for Concurrent Data Structures
Operating Systems Theory
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems
IEEE Transactions on Computers
Analytic modeling of channel traffic in n-cubes
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
| Hi-index | 14.98 |
Wormhole routing is an attractive routing technique offering low latency communication without the need to buffer an entire packet in a single node. A new queueing-theoretic model for obtaining throughput and latency of binary hypercubes supporting wormhole routing is developed here. The model is very accurate in predicting the performance of an actual multicomputer over a range of network sizes, packet lengths, and input port priority mappings. Utilizing the model, the performance of networks with identical topologies but different node architectures is estimated.