Parallel hashing—an efficient implementation of shared memory
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
Deterministic simulation of idealized parallel computers on more realistic ones
SIAM Journal on Computing
A probabilistic simulation of PRAMs on a bounded degree network
Information Processing Letters
Locality, communication, and interconnect length in multicomputers
SIAM Journal on Computing
A complexity theory of efficient parallel algorithms
Theoretical Computer Science - Special issue: Fifteenth international colloquium on automata, languages and programming, Tampere, Finland, July 1988
A bridging model for parallel computation
Communications of the ACM
Proceedings of the fifth MIT conference on Advanced research in VLSI
Journal of Computer and System Sciences
Parallel algorithms for shared-memory machines
Handbook of theoretical computer science (vol. A)
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Methods for message routing in parallel machines
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Efficient PRAM simulation on a distributed memory machine
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Reduction of network cost and wiring in Ranade's butterfly routing
Information Processing Letters
Simple, efficient shared memory simulations
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
General purpose parallel computing
Lectures on parallel computation
An optical simulation of shared memory
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
Dynamic Perfect Hashing: Upper and Lower Bounds
SIAM Journal on Computing
Are multiport memories physically feasible?
ACM SIGARCH Computer Architecture News
ICS '90 Proceedings of the 4th international conference on Supercomputing
Doubly Logarithmic Communication Algorithms for Optical-Communication Parallel Computers
SIAM Journal on Computing
Simulation-based Comparison of Hash Functions for Emulated Shared Memory
PARLE '93 Proceedings of the 5th International PARLE Conference on Parallel Architectures and Languages Europe
Simulation of PRAM Models on Meshes
PARLE '94 Proceedings of the 6th International PARLE Conference on Parallel Architectures and Languages Europe
Hashing Strategies for Simulating Shared Memory on Distributed Memory Machines
Proceedings of the First Heinz Nixdorf Symposium on Parallel Architectures and Their Efficient Use
Solving Fundamental Problems on Sparse-Meshes
IEEE Transactions on Parallel and Distributed Systems
A Hardware Implementation of PRAM and Its Performance Evaluation
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
ACM Transactions on Programming Languages and Systems (TOPLAS)
Recurrence equation as basis for designing hot-potato routing protocols
CompSysTech '04 Proceedings of the 5th international conference on Computer systems and technologies
Towards programming on the moving threads architecture
Proceedings of the 11th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing on International Conference on Computer Systems and Technologies
Address-free all-to-all routing in sparse torus
PaCT'07 Proceedings of the 9th international conference on Parallel Computing Technologies
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Memory access is the bottleneck in the simulation of shared memory on a distributed memory model. We show that EREW, CREW, and CRCW PRAM models can be simulated work-optimally on a mesh-connected routing machinery that is coated with processors. The simulation uses a combination of well-known techniques such as randomized hashing, greedy routing, and parallel slackness.The advantage of our mesh based simulation is the simple and scalable structure of the mesh combined with good performance. A theoretical analysis and practical experiments show that our simulation is economical and efficient in comparison with other proposed architectures, such as butterflies and hypercubes, for all feasible numbers of processors.