Communicating sequential processes
Communicating sequential processes
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Design and validation of computer protocols
Design and validation of computer protocols
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Safety-level communication in railway interlockings
Science of Computer Programming - Special issue on COST 247, verification and validation methods for formal descriptions
A Formal Verification Environment for Railway Signaling System Design
Formal Methods in System Design - Special issue: industrial critical systems
The Byzantine Generals Problem
ACM Transactions on Programming Languages and Systems (TOPLAS)
Applying Formal Specification in Industry
IEEE Software
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Guarded commands, non-determinacy and a calculus for the derivation of programs
Proceedings of the international conference on Reliable software
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Parallel Model Checking for the Alternation Free µ-Calculus
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
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This paper describes an experience in formal specification and fault tolerant behavior validation of a railway critical system. The work, performed in the context of a real industrial project, had the following main targets: (a) to validate specific safety properties in the presence of byzantine system components or of some hardware temporary faults; (b) to design a formal model of a critical railway system at a right level of abstraction so that could be possible to verify certain safety properties and at the same time to use the model to simulate the system. For the model specification we used the PROMELA language, while the verification was performed using the SPIN model checker. Safety properties were specified by means of both assertions and temporal logic formulae. To make the problem of validation tractable in the SPIN environment, we used ad hoca bstraction techniques.