Algebraic laws for nondeterminism and concurrency
Journal of the ACM (JACM)
Decision procedures and expressiveness in the temporal logic of branching time
Journal of Computer and System Sciences
Communicating sequential processes
Communicating sequential processes
“Sometimes” and “not never” revisited: on branching versus linear time temporal logic
Journal of the ACM (JACM) - The MIT Press scientific computation series
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Communication and concurrency
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
An action-based framework for verifying logical and behavioural properties of concurrent systems
Computer Networks and ISDN Systems - Special issue on tools for FDTs
Verification in process algebra of the distributed control of track vehicles—a case study
Formal Methods in System Design
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Seven More Myths of Formal Methods
IEEE Software
AUTO: A Verification Tool for Distributed Systems Using Reduction of Finite Automata Networks
FORTE '89 Proceedings of the IFIP TC/WG6.1 Second International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols
Linear and Branching Structures in the Semantics and Logics of Reactive Systems
Proceedings of the 12th Colloquium on Automata, Languages and Programming
Verifying hardware components within JACK
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Concurrency and Automata on Infinite Sequences
Proceedings of the 5th GI-Conference on Theoretical Computer Science
Formal Methods in the Railways Signalling Industry
FME '94 Proceedings of the Second International Symposium of Formal Methods Europe on Industrial Benefit of Formal Methods
A Formal Specification of an Automatic Train Protection System
FME '94 Proceedings of the Second International Symposium of Formal Methods Europe on Industrial Benefit of Formal Methods
Automatic Verification of a Hydroelectric Power Plant
FME '96 Proceedings of the Third International Symposium of Formal Methods Europe on Industrial Benefit and Advances in Formal Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Symbolic Bisimulation Minimisation
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
A Case Study in Safety-Critical Design
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Automatic verification of industrial designs
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Verification of a Radio-Based Signaling System Using the STATEMATE Verification Environment
Formal Methods in System Design
A Formal Specification and Validation of a Critical System in Presence of Byzantine Errors
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Formal Validation of the GUARDS Inter-Consistency Mechanism
SAFECOMP '99 Proceedings of the 18th International Conference on Computer Computer Safety, Reliability and Security
A Symbolic Model Checker for ACTL
FM-Trends 98 Proceedings of the International Workshop on Current Trends in Applied Formal Method: Applied Formal Methods
Instantiating generic charts for railway interlocking systems
Proceedings of the 10th international workshop on Formal methods for industrial critical systems
Experimenting with diversity in the model driven development of a railway signaling system
Proceedings of the 2007 workshop on Engineering fault tolerant systems
ACTLW - An action-based computation tree logic with unless operator
Information Sciences: an International Journal
Design and validation of variability in product lines
Proceedings of the 2nd International Workshop on Product Line Approaches in Software Engineering
Formal safety proof: a real case study in a railway interlocking system
Proceedings of the 2013 International Symposium on Software Testing and Analysis
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A fundamental problem in the design and development of embeddedcontrol systems is the verification of safety requirements. Formal methods,offering a mathematical way to specify and analyze the behavior of asystem, together with the related support tools can successfully beapplied in the formal proof that a system is safe. However, the complexityof real systems is such that automated tools often fail to formallyvalidate such systems.This paper outlines an experience on formal specification andverification carried out in a pilot project aiming at the validation of arailway computer based interlocking system. Both the specification and theverification phases were carried out in the JACK (Just Another ConcurrencyKit) integrated environment. The formal specification of the system was doneby means of process algebra terms. The formal verification of the safetyrequirements was done first by giving a logical specification of such safetyrequirements, and then by means of model checking algorithms. Abstractiontechniques were defined to make the problem of safety requirementsvalidation tractable by the JACK environment.