A successful attack against the DES
Proceedings of the third Canadian workshop on Information theory and applications
Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
Cryptography: Theory and Practice
Cryptography: Theory and Practice
Handbook of Applied Cryptography
Handbook of Applied Cryptography
A High-Speed DES Implementation for Network Applications
CRYPTO '92 Proceedings of the 12th Annual International Cryptology Conference on Advances in Cryptology
A case study of partially evaluated hardware circuits: Key-specific DES
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Functional Design Using Behavioural and Structural Components
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Experience Using a Low-Cost FPGA Design to Crack DES Keys
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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Most modern security protocols and security applications are defined to be algorithm independent, that is, they allow a choice from a set of cryptographic algorithms for the same function. Although an algorithm switch is rather difficult with traditional hardware, i.e., ASIC, implementations, Field Programmable Gate Arrays (FPGAs) offer a promising solution. Similarly, an ASIC-based key search machine is in general only applicable to one specific encryption algorithm. However, a key-search machine based on FPGAs can also be algorithm independent and thus be applicable to a wide variety of ciphers. We researched the feasibility of a universal key-search machine using the Data Encryption Standard (DES) as an example algorithm. We designed, implemented and compared various architecture options of DES with strong emphasis on high-speed performance. Techniques like pipelining and loop unrolling were used and their Effectiveness for DES on FPGAs investigated. The most interesting result is that we could achieve encryption rates beyond 400 Mbit/s using a standard Xilinx FPGA. This result is by a factor of about 30 faster than software implementations while we are still maintaining flexibility. A DES cracker chip based on this design could search 6.29 million keys per second.