The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Efficient hardware implementation of the DES
Proceedings of CRYPTO 84 on Advances in cryptology
Modern cryptology
Gallium Arsenide Computer Design
Gallium Arsenide Computer Design
Differential Cryptanalysis of the Full 16-Round DES
CRYPTO '92 Proceedings of the 12th Annual International Cryptology Conference on Advances in Cryptology
CCS '96 Proceedings of the 3rd ACM conference on Computer and communications security
How to decrypt or even substitute DES-Encrypted messages in 228 steps
Information Processing Letters
Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine
SAC '98 Proceedings of the Selected Areas in Cryptography
IEEE Transactions on Computers
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security
The Journal of Supercomputing
Accelerating memory decryption and authentication with frequent value prediction
Proceedings of the 4th international conference on Computing frontiers
A simple and efficient key exchange scheme against the smart card loss problem
EUC'07 Proceedings of the 2007 conference on Emerging direction in embedded and ubiquitous computing
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A high-speed data encryption chip implementing the Data Encryption Standard (DES) has been developed. The DES modes of operation supported are Electronic Code Book and Cipher Block Chaining. The chip is based on a gallium arsenide (GaAs) gate array containing 50K transistors. At a clock frequency of 250 MHz, data can be encrypted or decrypted at a rate of 1 GBit/second, making this the fastest single-chip implementation reported to date. High performance and high density have been achieved by using custom-designed circuits to implement the core of the DES algorithm. These circuits employ precharged logic, a methodology novel to the design of GaAs devices. A pipelined flow-through architecture and an efficient key exchange mechanism make this chip suitable for low-latency network controllers.