Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Model checking in industrial hardware design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
Formal Development of Reactive Systems - Case Study Production Cell
Formal Development of Reactive Systems - Case Study Production Cell
Improving System Reliability with Automatic Fault Tree Generation
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Timing analysis of industrial real-time systems
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
IEEE Transactions on Computers
Model Checking Support for the ASM High-Level Language
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
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Formal risk analysis (FRA) is a means for automatic generation of fault trees for failures of sensors, actuators, and other input and output devices. FRA can be used to automate significant parts of the manual fault tree analysis work, and hence automate the proof of fail-safe behavior. Because FRA is based on information that is already used for formal verification, no additional effort is necessary for the automatic generation of fault trees with FRA. While formal verification focuses on the functional aspects, in particular safety functions, the fault tree analysis with FRA focuses on the system integrity. FRA significantly reduces the effort for the generation of fault trees. This paper describes Formal Risk Analysis and its application for the proof of fail-safe behavior.