Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Optimization
Architecture and programming of two generations of video signal processors
Microprocessing and Microprogramming - Special issue: parallel programmable architectures and compilation
Local Search in Combinatorial Optimization
Local Search in Combinatorial Optimization
Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal Processors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Delay Management for Programmable Video Signal Processors
EDTC '97 Proceedings of the 1997 European conference on Design and Test
IEEE Transactions on Signal Processing
Cheops: a reconfigurable data-flow system for video processing
IEEE Transactions on Circuits and Systems for Video Technology
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We consider the problem of mapping video algorithms onto systems of high-performance video signal processors with hard real-time constraints. The mapping problem under consideration is computationally hard due to the many constraints that need to be satisfied. We present a compact mathematical formulation which identifies the decision variables and the constraints that are involved. We demonstrate that the mapping problem is NP-hard in the strong sense. The insight resulting from the mathematical formulation leads to a solution approach in which the problem is decomposed into subproblems called delay management, partitioning, and scheduling. These subproblems are handled with well-known techniques from the literature such as network flow, local search, and constraint satisfaction.