Delay Management for Programmable Video Signal Processors

Authors:
M. L. G. Smeets;E. H. L. Aarts;G. Essink;E. A. de Kock
Affiliations:
Philips Research, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;Philips Research, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;Philips Research, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;Philips Research, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

Citing 5
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Abstract

We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The corresponding delay management problem is proved to be NP-hard. We present a solution strategy that decomposes the delay management problem into a delay minimization problem followed by a delay assignment problem. The delay minimization problem is solved with network flow techniques. The delay assignment problem is handled by a constructive approach. The performance of the combined approach is analyzed by means of a benchmark set of industrially relevant video algorithms.