Dynamic Optimisation of Non-linear Feed Forward Circuits
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
Evolvable hardware a new approach for control design
EC'06 Proceedings of the 7th WSEAS International Conference on Evolutionary Computing
Branch predictor on-line evolutionary system
Proceedings of the 10th annual conference on Genetic and evolutionary computation
ACMOS'08 Proceedings of the 10th WSEAS International Conference on Automatic Control, Modelling & Simulation
Research on multi-objective on-line evolution technology of digital circuit based on FPGA model
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
An evolutionary approach to ontology-based user model acquisition
WILF'03 Proceedings of the 5th international conference on Fuzzy Logic and Applications
Packet classification with evolvable hardware hash functions – an intrinsic approach
BioADIT'06 Proceedings of the Second international conference on Biologically Inspired Approaches to Advanced Information Technology
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An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16- bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. An experimental study is carried out to determine the best set of parameters for on-line execution. It is observed that small population size leads to more effective results when short execution time is required. An application of the evolutionary approach presented in the paper for on-line tuning of the function during cache memory operation is also discussed.