AUTO CARD automated printed circuit board design
DAC '64 Proceedings of the SHARE design automation workshop
Clustering and linear placement
25 years of DAC Papers on Twenty-five years of electronic design automation
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Layout design—lessons from the Jedi designer (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
ALMS: Automated logic mapping system
DAC '71 Proceedings of the 8th Design Automation Workshop
A logic partitioning procedure by interchanging clusters
DAC '75 Proceedings of the 12th Design Automation Conference
A new fuzzy-clustering-based approach for two-way circuit partitioning
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Program restructuring for virtual memory
IBM Systems Journal
Lower bounds for the partitioning of graphs
IBM Journal of Research and Development
Multilevel optimization for large-scale hierarchical FPGA placement
Journal of Computer Science and Technology
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This paper presents a technique for dividing a network of interconnecting components into groups of components so that the total number of interconnecting wires between groups tends to be minimized. The method of solution is noniterative, and provides good solutions using small amounts of computer time. The solution is based on the use of an electrical analogue which may be useful in aiding other design automation tasks.