A performance counter architecture for computing accurate CPI components
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Automated design of application specific superscalar processors: an analytical approach
Proceedings of the 34th annual international symposium on Computer architecture
Toward a multicore architecture for real-time ray-tracing
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A mechanistic performance model for superscalar out-of-order processors
ACM Transactions on Computer Systems (TOCS)
Studying compiler optimizations on superscalar processors through interval analysis
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
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With advances in semiconductor technology, processorsare becoming larger and more complex. Future processordesigners will face an enormous design space, and mustevaluate more architecture design points to reach a finaloptimum design. This exploration is currently performedusing cycle accurate simulators that are accurate but slow,limiting a comprehensive search of design options. The vastdesign space and time to market economic pressures motivatethe need for faster architectural evaluation methods.The model presented in this paper facilitates a rapid exploration of the architecture design space for superscalarprocessors. It supplements current design tools by narrowinga large design space quickly, after which existing cycleaccurate simulators can arrive at a precise optimum design.This allows a designer to select the final architecturedesign much faster than with traditional tools. The modelcalculates the instruction throughput of superscalar processorsusing a set of key architecture and application properties.It was validated with the Simplescalar out-of-ordersimulator. Results were within 5.5% accuracy of the cycleaccurate simulator, but executed 40,000 times faster.