ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A Low-Loss Built-In Current Sensor
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
IC test using the energy consumption ratio
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fault models and test generation for IDDQ testing: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Analyzing the Need for ATPG Targeting GOS Defects
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
AN IDDQ SENSOR CIRCUIT FOR LOW-VOLTAGE ICS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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In a previous work on test generation for IDDQ bridging faults in CMOS circuits, a genetic algorithm (GA) based approach targeting the all-pair bridging fault set stored in a compact-list data structure was used. In this paper, we target a reduced fault set, such as the one extracted from circuit layout. The reduced fault set is O(N) versus O(N^2) for the all-pair set, where N is the number of nodes in the transistor netlist. For test generation purposes, a linear-list data structure is found to be more efficient than the compact-list when a reduced fault list is targeted. We report on results for benchmark circuits that illustrate that test generation using a reduced fault list takes less time and results in more compact IDDQ test sets with higher fault coverage of targeted bridging faults. The effects of GA sequence lengths on test generation times and test set quality are also considered.